Quantum error correction (QEC) is often discussed as if it were a single technology that hardware platforms either do or do not support. In reality, different QEC codes have different connectivity requirements, different ancilla overhead, different syndrome extraction circuits, and different sensitivities to the specific error models of the underlying hardware. The right code for a neutral-atom tweezer array is not necessarily the same as the right code for a superconducting processor or a trapped-ion chain. This post surveys the main QEC approaches and assesses how they map onto neutral-atom hardware in its current form.
The surface code: well-studied, demanding on two-qubit gate fidelity
The surface code has become the dominant near-term QEC target for most platforms because of two key properties: high threshold gate error rate (approximately 1%) and low connectivity requirements (each qubit interacts only with its four nearest neighbors in a 2D grid). For neutral-atom systems with reconfigurable tweezer arrays and 2D spatial layouts, the connectivity requirement is naturally satisfied.
The surface code threshold of approximately 1% was derived under the assumption that all errors are independent depolarizing noise. Neutral-atom gate errors are not purely depolarizing. They include correlated errors from Rydberg blockade crosstalk (when a Rydberg excitation partially affects neighboring atoms), and leakage errors when atoms occasionally leave the computational subspace. Both of these error types are worse for the surface code than an equivalent amount of depolarizing noise, because they can generate multi-qubit correlated error patterns that the surface code decoder has difficulty distinguishing from benign syndrome patterns.
The leakage issue is particularly acute. Standard surface code decoders assume two-level qubits. A neutral-atom qubit that has leaked to a third level produces an error pattern that looks like simultaneous X and Z errors to a standard decoder, which it attributes (incorrectly) to a depolarizing event and may misidentify in the minimum-weight matching algorithm. Leakage-aware decoders that track leakage as a distinct error type improve the effective threshold, but require more complex real-time decoding hardware.
Given current neutral-atom two-qubit gate fidelity in the 98-99.5% range, the surface code threshold is marginally accessible. Whether any given system is above or below threshold depends strongly on the leakage rate and the decoder implementation. Our current platform is not positioned to run surface code at fault-tolerant scale, but we view it as a realistic target for a 256-qubit system with improved two-qubit gate fidelity.
Flag-qubit protocols: lower qubit overhead for specific codes
Flag-qubit protocols are a family of syndrome measurement techniques developed specifically to reduce the ancilla overhead needed to detect hook errors in fault-tolerant circuits. In a standard Steane or CSS code syndrome extraction, each ancilla measures stabilizers by interacting with multiple data qubits in sequence. If the ancilla experiences an error during this sequence, it can spread the error to multiple data qubits, a "hook error" that may produce a logical error that standard threshold calculations do not account for. The conventional solution is to add more ancilla qubits to verify the syndrome measurements, increasing qubit overhead.
Flag-qubit protocols instead use a single "flag" ancilla that is designed to trigger if and only if a hook error has occurred during the syndrome measurement. This reduces the overhead dramatically in specific code families. For a [[7,1,3]] Steane code, a flag-qubit protocol can achieve fault tolerance with only a few additional ancilla qubits rather than the full overhead of a code concatenation approach.
For neutral-atom systems, flag-qubit protocols are interesting for a different reason: they require mid-circuit ancilla measurements, which neutral-atom systems handle naturally via fluorescence imaging on the cooling transition without disturbing qubits in the clock state. This mid-circuit measurement capability is a genuine advantage over superconducting systems for certain QEC protocols, because it allows ancilla reset and reuse within a circuit without requiring separate registers or transport. The flag-qubit approach exploits this capability directly.
Erasure conversion: turning leakage into a resource
An "erasure" error is a loss event with a known location: you know which qubit was lost, but you do not know the state it had. Erasure errors are significantly easier to correct than unknown Pauli errors because the syndrome measurement is contaminated only at the known erasure location, which constrains the decoder's search space substantially. QEC codes can tolerate erasure error rates roughly twice as high as depolarizing error rates at the same code distance.
Neutral-atom systems have a natural leakage channel that can be converted to erasure with appropriate detection. When a strontium-88 qubit in the 3P0 clock state decays back to the ground state (a rare but non-zero event), the decayed atom stops responding to the Rydberg excitation sequence and can be detected by a fluorescence imaging check after each gate layer. This detection turns what would have been an unheralded leakage error into a known erasure at a known site. The decoder then treats the erased site with an erasure model rather than a depolarizing model, which improves the effective threshold.
The erasure conversion approach has been explored theoretically and in small-scale experimental demonstrations in the field. For it to be practical at circuit scale, the fluorescence check must be fast enough not to dominate the circuit runtime. In our system, a full-array fluorescence image takes approximately 30 ms, which is acceptable as a per-layer check for shallow circuits but represents significant overhead for deep circuits with many gate layers. We are working on a partial-array imaging approach that checks only a high-risk subset of qubits per layer to reduce this overhead.
What our platform currently supports for QEC research
Our 100-qubit system is not running fault-tolerant computation; we want to be direct about that. The current gate fidelity is insufficient for full surface-code operation without active error correction consuming more resources than it saves. What we do support is QEC research at the physical and logical layer.
We can run small-distance surface code experiments (distance 3 and distance 5) to characterize the error model and test decoder implementations against real hardware noise. The reconfigurable tweezer geometry is well-suited for running the same logical circuit under different physical qubit connectivity arrangements, which is useful for comparing stabilizer code variants. And the mid-circuit measurement capability supports flag-qubit and erasure-based protocols at small scale.
A research group running QEC experiments on our platform is not doing fault-tolerant quantum computation. They are characterizing error models, testing decoder algorithms against realistic physical noise, and exploring how neutral-atom-specific error channels (leakage, Rydberg crosstalk, atom loss) interact with different code structures. Those are legitimate and valuable research activities that inform the path toward fault-tolerant operation on future hardware generations.
We are not claiming our current platform is ready for fault-tolerant computation. We are saying it is a useful tool for the QEC research that must be done before fault-tolerant platforms exist. That is a different value proposition, and it is the honest one.